Mobile communication devices utilize multiple types of receivers. When the radio frequency (RF) spectrum is directly translated to the baseband in the first down-conversion, the receiver is called a “homodyne,” “direct-conversion,” or “Zero-IF” architecture.
FIG. 1 is a block diagram of a typical zero-IF receiver circuit 100.
Receiver circuit 100 includes antenna 101 which is coupled to an input terminal of band pass filter 102. The output terminal of band pass filter 102 is coupled to the input terminal of low-noise amplifier (LNA) 104. The output of LNA 104 is coupled to the input terminals of mixer 108 and mixer 114. The output terminals of mixers 108 and 114 are coupled to the input terminals of low pass filter elements 110 and 116, respectively.
Low pass filter elements 110 and 116 together comprise a single, simple low pass filter with independent in-phase (I) and quadrature (Q) path circuits, respectively.
The output terminals of low pass filter elements 110 and 116 are coupled to the input terminals of variable gain amplifiers (VGA) 112 and 118, respectively. The output terminal of VGA 112 contains the in-phase (I) channel signal. Alternatively, the output terminal of VGA 118 contains the quadrature (Q) channel signal.
Radio frequency (RF) voltage controlled oscillator (VCO) 120 provides a reference frequency and is coupled to the input terminal of phase selector 106. A first output terminal of phase selector 106 is coupled to a second input terminal of mixer 108. The first output terminal of phase selector 106 provides a zero degree phase shift of the RF VCO signal. The second output terminal of phase selector 106 is coupled to a second input of mixer 114. The second output terminal of phase selector 106 provides a 90 degree phase shift of the RF VCO signal.
The difference between a zero-IF and a low-IF receiver is the down-conversion process. In a zero-IF receiver, the wanted channel is directly converted to DC, which offers two advantages. First, the problem of image rejection is circumvented because WIF=0. Thus, the need for image rejection is reduced.
Second, IF filters and subsequent down-conversion stages are replaced with low-pass filters and baseband amplifiers, which are amenable to be integrated in Complementary Metal-Oxide Semiconductor (CMOS) technology. While zero-IF architecture increases simplicity, certain characteristics of the zero-IF receiver are of paramount importance. One such characteristic is direct current (DC) offset voltage.
DC offset voltage results from two main factors. The first factor is the finite isolation between the local oscillator (LO) port with the inputs of the mixer and the low-noise amplifier (LNA). The leakage signal appearing at the input of LNA and the mixer are mixed with the LO signal, producing a DC component. This phenomenon is called “self-mixing”. The offset voltages corrupt the signal and saturate the subsequent stages.
The feedback mechanisms for the digital circuitry to the analog front-end circuitry compensate for the DC offset to some extent. However, because a feedback loop has a finite time-constant, part of the signal contents are canceled by the loop, thus degrading signal quality.
The second factor is even-order distortion. Typical RF receivers are susceptible to only odd-order intermodulation effects. However, in a direct-conversion architecture, even-order distortion is an issue. FIG. 2 is a block diagram showing how feedthrough contributes to even-order distortion.
As illustrated in FIG. 2, two strong interferers close to the channel of interest experience nonlinearity in the LNA, which may be expressed as,y(t)=α1x(t)+a2x2(t)  Eq. (1)If x(t) isx(t)=A1 cos ω1t+A2 cos ω2t  Eq. (2)Thus, y(t) contains a term,α2A1A2 cos (ω1−ω2)t  Eq. (3)indicating that two high-frequency interferers generate a low-frequency beat in the presence of even-order distortion.
Referring to FIG. 2, the output terminal of LNA 202 is coupled to the input terminal of mixer 204. The output terminal of mixer 204, in turn, is coupled to the input terminal of low pass filter element 206.
In an ideal mixer, the low-frequency beat is translated to high frequencies and hence become unimportant after filtering. In reality however, a mixer exhibits a finite direct feed through from an RF port to an IF port due to element mismatch. Thus, the mixer is not ideal and produces an output signal such as,vin(t)(a+A cos ωLOt).  Eq. (4)
The low-frequency beat that appears at the output of the mixer with no frequency translation can corrupt the down-converted signal of interest. In order to eliminate, or at least significantly reduce these unwanted effects, direct current (DC) offset calibration is provided.
DC offset calibration aims to adjust the output signal of each low pass filter element to a DC voltage approximately equal to zero volts.
A known technique of DC offset calibration for a simple low pass filter involves injecting correction currents at the input of each low pass filter element to drive the output voltage to approximately zero volts. In a simple low pass filter configuration, current injection is performed on the In-Phase (I) and Quadrature (Q) paths independently.
FIG. 3 is a circuit diagram of a typical simple low pass filter with DC offset calibration. In this example configuration, low pass filter 300 comprises a first calibration path circuit 300a and a second calibration path circuit 300b, each of which may correspond to low pass filter elements 110 and 116 shown in FIG. 1.
Here, the output terminal VoI of operational amplifier 302 is coupled to a first terminal of resistor 304. A second terminal of resistor 304 is coupled to the negative input of operational amplifier 302. The output terminal VoQ of operational amplifier 312 is coupled to a first terminal of resistor 314. A second terminal of resistor 314 is coupled to the negative input of operational amplifier 312. VosI and VosQ are offset voltages of operational amplifiers 302 and 312, respectively. Voltage VosI is represented by voltage source 306. VosQ is represented by voltage source 320. Voltage source operational amplifier 302 is in the I channel path. Operational amplifier 312 is in the Q channel path. Offset current due to mixer 108, shown in FIG. 1, may be modeled as current source 310, which provides current iosI. Offset current due to mixer 114, shown in FIG. 1, may be modeled as current source 316, which provides current iosQ. The effect of these offset sources is to generate an erroneous DC offset voltage at the output terminals of the filter, VoI and VoQ respectively. By injecting correction currents iosI′ and iosQ′ the DC voltage on output terminals VoI and VoQ may be reduced to approximately zero volts. Correction current iosI′ is modeled by current source 308. Correction current iosQ′ is modeled by current source 318.
When correction current sources are set to zero amperes, the I channel output voltage VoI may be expressed as,VoI=(VosI−iosI*Rf)  Eq. (5)and Q channel output voltage VoQ may be expressed as,VoQ=(VosQ−iosQ*Rf)  Eq. (6)Therefore, to calibrate the output voltages to zero volts I channel current correction current iosI′ can be set to,iosI′=iosI−(VosI/Rf)  Eq. (7)and Q channel current correction current iosQ′ can be set to,iosQ′=iosQ−(VosQ/Rf)  Eq. (8)The injection of correction currents iosI′ and iosQ′ drive output voltages VoI and VoQ to zero, thus correcting for DC offset voltage at the output of the filter. Because there are two independent I and Q paths, two separate DC offset calibrations are typically required to remove the respective DC offset voltage on each channel path.
FIG. 4 is a further circuit diagram of a typical complex low pass filter 400 comprised of cross-switched I and Q paths. In the example configuration, low pass filter 400 includes a first calibration path circuit 400a and a second calibration path circuit 400b which together define the respective I and Q paths of low pass filter 400.
Here, operational amplifier 402 output terminal VoI is coupled to a first terminal of resistor 404. A second terminal of resistor 404 is coupled to the negative input of operational amplifier 402. Operational amplifier 402 output terminal VoI is switchably coupled to a first terminal of coupling resistor 413 through switch 417. A second terminal of coupling resistor 413 is coupled to the negative terminal of operational amplifier 412. Operational amplifier 412 output terminal VoQ is coupled to a first terminal of resistor 414. A second terminal of resistor 414 is coupled to the negative input of operational amplifier 412. Operational amplifier 412 output terminal VoQ is switchably coupled to a first terminal of inverter 405 through switch 407. A second terminal of inverter 405 is coupled to a first terminal of coupling resistor 403.
In a single-ended configuration as shown, inverter 405 is necessary to provide the change in polarity required to create a complex filer frequency response.
When utilizing differential circuits the inverter 405 is sometimes omitted because the required change in polarity may be created by connecting the first differential circuit positive output to the second differential circuit negative input and coupling the first differential circuit negative output to the positive input of the second differential circuit.
Referring again to FIG. 4, a second terminal of coupling resistor 403 is coupled to the negative input terminal of operational amplifier 402. VosI and VosQ are offset voltages of operational amplifiers 402 and 412, respectively. Voltage VosI is represented by voltage source 406. VosQ is represented by voltage source 420. Voltage source operational amplifier 402 is in the I channel path. Operational amplifier 412 is in the Q channel path. Offset current due to mixer 108, shown in FIG. 1, may be modeled as current source 410, which provides current iosI. Offset current due to mixer 114, shown in FIG. 1, may be modeled as current source 416, which provides current iosQ. The effect of these offset sources is to generate an erroneous DC offset voltage at the output terminals of the filter, VoI and VoQ respectively. By injecting correction currents iosI′ and iosQ′ the DC voltage on output terminals VoI and VoQ may be reduced to approximately zero volts. Correction current iosI′ is modeled by current source 408. Correction current iosQ′ is modeled by current source 418.
FIG. 6 is a flow chart describing the operation of the typical complex filter configuration circuit shown in FIG. 4.
The flow begins in step 600. Switches 407 and 417, shown in FIG. 4, are then opened in step 602. Correction current sources 408 and 418 are then adjusted to set the output terminals VoI and VoQ of the filter to zero volts DC in step 604. Once the output terminals VoI and VoQ have been calibrated to zero volts, switches 407 and 417 are closed in step 606. Then normal operation begins in step 608. The process is then completed in step 610. It is herein noted, that it may be necessary to perform this correction procedure multiple times to reduce the DC offset voltage (due to associated transients) below a given threshold value.
There is a need for improved DC offset calibration for complex filters which can drive the output DC voltage sufficiently close to zero volts in a minimal number of iterations.